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Freescale Semiconductor /MK24F12 /CAN0 /CTRL1

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Interpret as CTRL1

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0PROPSEG 0 (0)LOM 0 (0)LBUF 0 (0)TSYN 0 (0)BOFFREC 0 (0)SMP 0 (0)RWRNMSK 0 (0)TWRNMSK 0 (0)LPB 0 (0)CLKSRC 0 (0)ERRMSK 0 (0)BOFFMSK 0PSEG20PSEG10RJW0PRESDIV

BOFFREC=0, LOM=0, CLKSRC=0, RWRNMSK=0, LBUF=0, TWRNMSK=0, TSYN=0, ERRMSK=0, BOFFMSK=0, LPB=0, SMP=0

Description

Control 1 register

Fields

PROPSEG

Propagation Segment
LOM

Listen-Only Mode

0 (0): Listen-Only mode is deactivated.

1 (1): FlexCAN module operates in Listen-Only mode.
LBUF

Lowest Buffer Transmitted First

0 (0): Buffer with highest priority is transmitted first.

1 (1): Lowest number buffer is transmitted first.
TSYN

Timer Sync

0 (0): Timer Sync feature disabled

1 (1): Timer Sync feature enabled
BOFFREC

Bus Off Recovery

0 (0): Automatic recovering from Bus Off state enabled, according to CAN Spec 2.0 part B.

1 (1): Automatic recovering from Bus Off state disabled.
SMP

CAN Bit Sampling

0 (0): Just one sample is used to determine the bit value.

1 (1): Three samples are used to determine the value of the received bit: the regular one (sample point) and 2 preceding samples; a majority rule is used.
RWRNMSK

Rx Warning Interrupt Mask

0 (0): Rx Warning Interrupt disabled.

1 (1): Rx Warning Interrupt enabled.
TWRNMSK

Tx Warning Interrupt Mask

0 (0): Tx Warning Interrupt disabled.

1 (1): Tx Warning Interrupt enabled.
LPB

Loop Back Mode

0 (0): Loop Back disabled.

1 (1): Loop Back enabled.
CLKSRC

CAN Engine Clock Source

0 (0): The CAN engine clock source is the oscillator clock. Under this condition, the oscillator clock frequency must be lower than the bus clock.

1 (1): The CAN engine clock source is the peripheral clock.
ERRMSK

Error Mask

0 (0): Error interrupt disabled.

1 (1): Error interrupt enabled.
BOFFMSK

Bus Off Mask

0 (0): Bus Off interrupt disabled.

1 (1): Bus Off interrupt enabled.
PSEG2

Phase Segment 2
PSEG1

Phase Segment 1
RJW

Resync Jump Width
PRESDIV

Prescaler Division Factor

Links

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Register License

Redistribution and use in source and binary forms, with or without modification,\nare permitted provided that the following conditions are met:\n o Redistributions of source code must retain the above copyright notice, this list\n of conditions and the following disclaimer.\n o Redistributions in binary form must reproduce the above copyright notice, this\n list of conditions and the following disclaimer in the documentation and/or\n other materials provided with the distribution.\n o Neither the name of Freescale Semiconductor, Inc. nor the names of its\n contributors may be used to endorse or promote products derived from this\n software without specific prior written permission.\n THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS “AS IS” AND\n ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED\n WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE\n DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR\n ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES\n (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;\n LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON\n ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS\n SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

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Register Reference

https://github.com/cmsis-svd/cmsis-svd-data